A TFT array substrate is disclosed. The substrate includes a TFT having a gate insulation layer, and an active layer partly thereon. The TFT also has a first part of an etch barrier layer on the active layer, and a source and drain on the first part of the etch barrier layer. The substrate also includes a capacitance having a first electrode plate, a second part of the gate insulation layer on the first electrode plate, a second part of the etch barrier layer on the second part of the gate insulation layer, and a second electrode plate on the second part of the etch barrier layer. The second part of the etch barrier layer has a thickness less than the first part of the etch barrier layer, and/or there is no etch barrier layer between the second part of the gate insulation layer and the second electrode plate.