发明授权
US09294120B2 Digital technique for excess loop delay compensation in a continuous-time delta sigma modulator
有权
用于连续时间ΔΣ调制器中多余环路延迟补偿的数字技术
- 专利标题: Digital technique for excess loop delay compensation in a continuous-time delta sigma modulator
- 专利标题(中): 用于连续时间ΔΣ调制器中多余环路延迟补偿的数字技术
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申请号: US14822061申请日: 2015-08-10
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公开(公告)号: US09294120B2公开(公告)日: 2016-03-22
- 发明人: Yi Zhang , Phillip Elliott , Ed Liu , Yang Qian , Geir Ostrem , John Frank Scampini
- 申请人: Maxim Integrated Products, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Maxim Integrated Products, Inc.
- 当前专利权人: Maxim Integrated Products, Inc.
- 当前专利权人地址: US CA San Jose
- 主分类号: H03M3/00
- IPC分类号: H03M3/00
摘要:
A continuous time delta sigma modulator includes a quantizer, a buffer module, and a reference module. The quantizer includes a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module receives the digital output, stores the digital output for a predetermined delay period, and outputs the digital output after the predetermined delay period as a delayed digital output. The predetermined delay period is less than one cycle of the clock signal. The reference module selectively varies the reference potential based on the delayed digital output.
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