发明授权
- 专利标题： Managing cache memory in a parallel processing environment
- 专利标题（中）： 在并行处理环境中管理高速缓存
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申请号： US14154277申请日： 2014-01-14
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公开(公告)号： US09298618B1公开(公告)日： 2016-03-29
- 发明人: David Wentzlaff , Matthew Mattina , Anant Agarwal
- 申请人： Matthew Mattina
- 申请人地址： US MA Westborough
- 专利权人： Tilera Corporation
- 当前专利权人： Tilera Corporation
- 当前专利权人地址： US MA Westborough
- 代理机构： Fish & Richardson P.C.
- 主分类号： G06F15/163
- IPC分类号： G06F15/163 ; G06F12/08 ; G06F12/10
摘要：
An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
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