Invention Grant
- Patent Title: Instruction cache having a multi-bit way prediction mask
- Patent Title (中): 具有多位方式预测掩码的指令高速缓存
-
Application No.: US13721317Application Date: 2012-12-20
-
Publication No.: US09304932B2Publication Date: 2016-04-05
- Inventor: Peter G. Sassone , Suresh K. Venkumahanti , Lucian Codrescu
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Paul Holdaway
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F9/38
Abstract:
In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.
Public/Granted literature
- US20140181405A1 INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK Public/Granted day:2014-06-26
Information query
