Invention Grant
US09305938B2 Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
有权
制造集成结构的方法，以及形成垂直堆叠的存储单元的方法
- Patent Title: Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
- Patent Title (中): 制造集成结构的方法，以及形成垂直堆叠的存储单元的方法
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Application No.: US14824942Application Date: 2015-08-12
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Publication No.: US09305938B2Publication Date: 2016-04-05
- Inventor: Fatma Arzum Simsek-Ege , Aaron R. Wilson
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/108
Abstract:
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.
Public/Granted literature
- US20150348991A1 Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells Public/Granted day:2015-12-03
Information query
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