Invention Grant
- Patent Title: Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
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Application No.: US14574855Application Date: 2014-12-18
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Publication No.: US09305997B1Publication Date: 2016-04-05
- Inventor: John H Zhang
- Applicant: STMICROELECTRONICS, INC.
- Applicant Address: US TX Coppell
- Assignee: STMICROELECTRONICS, INC.
- Current Assignee: STMICROELECTRONICS, INC.
- Current Assignee Address: US TX Coppell
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L49/02 ; H01L23/522 ; H01L21/768

Abstract:
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.
Information query
IPC分类: