Invention Grant
- Patent Title: Method and circuit for controlled gain reduction of a gain stage
- Patent Title (中): 增益级控制增益减小的方法和电路
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Application No.: US14191634Application Date: 2014-02-27
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Publication No.: US09306522B2Publication Date: 2016-04-05
- Inventor: Frank Kronmueller
- Applicant: Dialog Semiconductor GmbH
- Applicant Address: DE Kirchheim/Teck-Nabern
- Assignee: Dialog Semiconductor GmbH
- Current Assignee: Dialog Semiconductor GmbH
- Current Assignee Address: DE Kirchheim/Teck-Nabern
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Priority: EP13175998 20130710
- Main IPC: H03F3/45
- IPC: H03F3/45 ; H03G3/30 ; G05F1/56 ; H03G3/00 ; H03F1/34

Abstract:
The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described. The multi-stage amplifier comprises a first amplification stage configured to provide a stage output voltage at a stage output node. Furthermore, the amplifier comprises an intermediate amplification stage comprising an amplifier current source configured to provide an amplifier current and an amplifier transistor arranged in series with the amplifier current source. A gate of the amplifier transistor is coupled to the stage output node of the first amplification stage. The intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor.
Public/Granted literature
- US20150015332A1 Method and Circuit for Controlled Gain Reduction of a Gain Stage Public/Granted day:2015-01-15
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