Invention Grant
- Patent Title: Metallized via-holed ceramic substrate, and method for manufacture thereof
- Patent Title (中): 金属化的通孔陶瓷基板及其制造方法
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Application No.: US13710805Application Date: 2012-12-11
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Publication No.: US09307637B2Publication Date: 2016-04-05
- Inventor: Naoto Takahashi , Yasuyuki Yamamoto
- Applicant: TOKUYAMA CORPORATION
- Applicant Address: JP Shunan-shi, Yamaguchi
- Assignee: TOKUYAMA CORPORATION
- Current Assignee: TOKUYAMA CORPORATION
- Current Assignee Address: JP Shunan-shi, Yamaguchi
- Agency: Ladas & Parry LLP
- Priority: JP2012-013008 20120125
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/03 ; H05K3/00 ; H01L23/498 ; H01L23/15 ; H05K1/09 ; H01L33/62 ; H05K3/24 ; H05K3/40

Abstract:
The present invention provides a metallized via-holed ceramic substrate having (1) a sintered ceramic substrate, (2) an electroconductive via formed in the sintered ceramic substrate, having an electroconductive metal closely filled in a through-hole of the sintered ceramic substrate, wherein the electroconductive metal contains a metal (A) with melting point of 600° C. to 1100° C., a metal (B) with higher melting point than the metal (A), and an active metal, (3) a wiring pattern on at least one face of the sintered ceramics substrate, having an electroconductive surface layer and a plating layer thereon, wherein the electroconductive surface layer consists of an electroconductive metal containing the metal (A), the metal (B), and an active metal, (4) an active layer formed in the interface between the electroconductive via and the sintered ceramic substrate, and (5) an active layer formed in the interface between the electroconductive surface layer and the sintered ceramic substrate.
Public/Granted literature
- US20130186675A1 METALLIZED VIA-HOLED CERAMIC SUBSTRATE, AND METHOD FOR MANUFACTURE THEREOF Public/Granted day:2013-07-25
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