Invention Grant
- Patent Title: Semiconductor memory device controlling refresh cycle, memory system, and method of operating the semiconductor memory device
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Application No.: US14685912Application Date: 2015-04-14
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Publication No.: US09311987B2Publication Date: 2016-04-12
- Inventor: In-Chul Jeong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2012-0052593 20120517
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/406 ; G11C11/408

Abstract:
A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.
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