Invention Grant
- Patent Title: Protocol checking logic circuit for memory system reliability
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Application No.: US14593257Application Date: 2015-01-09
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Publication No.: US09317366B2Publication Date: 2016-04-19
- Inventor: David Wang
- Applicant: INPHI CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G06F11/10 ; G06F12/00 ; G06F11/00

Abstract:
A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.
Public/Granted literature
- US20150121133A1 PROTOCOL CHECKING LOGIC CIRCUIT FOR MEMORY SYSTEM RELIABILITY Public/Granted day:2015-04-30
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