Invention Grant
US09318214B2 Nonvolatile semiconductor memory device with a three-dimensional structure in which sub-blocks are independently erasable
有权
具有三维结构的非易失性半导体存储器件，其中子块是独立地可擦除的
- Patent Title: Nonvolatile semiconductor memory device with a three-dimensional structure in which sub-blocks are independently erasable
- Patent Title (中): 具有三维结构的非易失性半导体存储器件，其中子块是独立地可擦除的
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Application No.: US14015987Application Date: 2013-08-30
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Publication No.: US09318214B2Publication Date: 2016-04-19
- Inventor: Koji Hosono , Naoya Tokiwa
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2013-040525 20130301
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C11/56
Abstract:
A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block.
Public/Granted literature
- US20140247664A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2014-09-04
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