Invention Grant
- Patent Title: Method of stressing a semiconductor layer
- Patent Title (中): 强化半导体层的方法
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Application No.: US14526053Application Date: 2014-10-28
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Publication No.: US09318372B2Publication Date: 2016-04-19
- Inventor: Olivier Nier , Denis Rideau , Pierre Morin , Emmanuel Josse
- Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS , STMicroelectronics, Inc.
- Applicant Address: FR Montrouge FR Crolles US TX Coppell
- Assignee: STMicroelectronics SA,STMicroelectronics (Crolles 2) SAS,STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics SA,STMicroelectronics (Crolles 2) SAS,STMicroelectronics, Inc.
- Current Assignee Address: FR Montrouge FR Crolles US TX Coppell
- Agency: Seed IP Law Group PLLC
- Priority: FR1360673 20131031
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/762 ; H01L29/78 ; H01L27/12 ; H01L21/02

Abstract:
One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Public/Granted literature
- US20150118823A1 METHOD OF STRESSING A SEMICONDUCTOR LAYER Public/Granted day:2015-04-30
Information query
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