Invention Grant
US09318565B2 Power semiconductor device with dual field plate arrangement and method of making
有权
具有双场板布置的功率半导体器件和制造方法
- Patent Title: Power semiconductor device with dual field plate arrangement and method of making
- Patent Title (中): 具有双场板布置的功率半导体器件和制造方法
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Application No.: US14474051Application Date: 2014-08-29
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Publication No.: US09318565B2Publication Date: 2016-04-19
- Inventor: Hitoshi Kobayashi
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2014-052181 20140314
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L27/088 ; H01L21/8234 ; H01L21/3213 ; H01L29/417 ; H01L29/80 ; H01L29/49 ; H01L29/778 ; H01L29/20

Abstract:
A semiconductor device includes a semiconductor layer, gate electrodes, an insulating film, source electrodes, and drain electrodes which are provided on the semiconductor layer. Each of the source electrodes and the drain electrodes are spaced in the insulating film from a corresponding gate electrode, such that one end thereof is in contact with the semiconductor layer and the other end thereof is exposed. Further, the semiconductor device includes first field plate electrodes, each of which is provided on a corresponding gate electrode and the insulating film, and second field plate electrodes, each of which is provided on the insulating film between a corresponding first field plate electrode and a corresponding drain electrode. Furthermore, the thickness of the insulating film between each first field plate electrode and the semiconductor layer is smaller than the thickness of the insulating film between each second field plate electrode and the semiconductor layer.
Public/Granted literature
- US20150263107A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-09-17
Information query
IPC分类: