Invention Grant
US09318597B2 Layout configurations for integrating schottky contacts into a power transistor device
有权
用于将肖特基触点集成到功率晶体管器件中的布局配置
- Patent Title: Layout configurations for integrating schottky contacts into a power transistor device
- Patent Title (中): 用于将肖特基触点集成到功率晶体管器件中的布局配置
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Application No.: US14032995Application Date: 2013-09-20
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Publication No.: US09318597B2Publication Date: 2016-04-19
- Inventor: Vipindas Pala , Edward Robert Van Brunt , Lin Cheng , John Williams Palmour
- Applicant: Cree, Inc.
- Applicant Address: US NC Durham
- Assignee: Cree, Inc.
- Current Assignee: Cree, Inc.
- Current Assignee Address: US NC Durham
- Agent Anthony J. Josephson
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/47 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/16
Abstract:
A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.
Public/Granted literature
- US20150084119A1 LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE Public/Granted day:2015-03-26
Information query
IPC分类:
