Invention Grant
- Patent Title: Resistive memory cell having a reduced conductive path area
- Patent Title (中): 具有减小的导电路径面积的电阻式存储单元
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Application No.: US14184268Application Date: 2014-02-19
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Publication No.: US09318702B2Publication Date: 2016-04-19
- Inventor: Paul Fest , James Walls
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee Address: US AZ Chandler
- Agency: Slayden Grubert Beard PLLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.
Public/Granted literature
- US20150236258A1 RESISTIVE MEMORY CELL HAVING A REDUCED CONDUCTIVE PATH AREA Public/Granted day:2015-08-20
Information query
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