Invention Grant
- Patent Title: Flip-flop layout architecture implementation for semiconductor device
- Patent Title (中): 半导体器件的触发器布局架构实现
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Application No.: US14504075Application Date: 2014-10-01
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Publication No.: US09324715B2Publication Date: 2016-04-26
- Inventor: Raheel Azmat , Rwik Sengupta , Chulhong Park , Kwanyoung Chun
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2013-0160347 20131220
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L27/02 ; H01L21/8238
Abstract:
A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.
Public/Granted literature
- US20150179646A1 FLIP-FLOP LAYOUT ARCHITECTURE IMPLEMENTATION FOR SEMICONDUCTOR DEVICE Public/Granted day:2015-06-25
Information query
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