Invention Grant
US09330958B2 Process for fabricating a heterostructure limiting the formation of defects 有权
制造限制缺陷形成的异质结构的方法

  • Patent Title: Process for fabricating a heterostructure limiting the formation of defects
  • Patent Title (中): 制造限制缺陷形成的异质结构的方法
  • Application No.: US14360124
    Application Date: 2012-11-21
  • Publication No.: US09330958B2
    Publication Date: 2016-05-03
  • Inventor: Gweltaz Gaudin
  • Applicant: Soitec
  • Applicant Address: FR Bernin
  • Assignee: SOITEC
  • Current Assignee: SOITEC
  • Current Assignee Address: FR Bernin
  • Agency: TraskBritt
  • Priority: FR1161000 20111130
  • International Application: PCT/IB2012/002482 WO 20121121
  • International Announcement: WO2013/080010 WO 20130606
  • Main IPC: H01L21/30
  • IPC: H01L21/30 H01L21/762 H01L21/02 H01L21/265 H01L21/306 H01L21/324
Process for fabricating a heterostructure limiting the formation of defects
Abstract:
The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
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