Invention Grant
- Patent Title: Driver circuit with gate clamp supporting stress testing
- Patent Title (中): 驱动电路与门夹支持压力测试
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Application No.: US14449232Application Date: 2014-08-01
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Publication No.: US09331672B2Publication Date: 2016-05-03
- Inventor: Ni Zeng
- Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
- Applicant Address: CN Shenzhen
- Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
- Current Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
- Current Assignee Address: CN Shenzhen
- Agency: Gardere Wynne Sewell LLP
- Priority: CN201410320669 20140630; CN201420371939U 20140630
- Main IPC: H03B1/00
- IPC: H03B1/00 ; H03K3/00 ; H03K3/011 ; H03K17/687

Abstract:
A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.
Public/Granted literature
- US20150381148A1 DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING Public/Granted day:2015-12-31
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