Invention Grant
- Patent Title: Dicing wafers having solder bumps on wafer backside
- Patent Title (中): 切割晶片在晶片背面具有焊料凸块
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Application No.: US14543747Application Date: 2014-11-17
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Publication No.: US09343366B2Publication Date: 2016-05-17
- Inventor: Wei-Sheng Lei , James S. Papanu , Aparna Iyer , Brad Eaton , Ajay Kumar
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely Sokoloff Taylor Zafman LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/78 ; H01L21/683 ; H01L21/268 ; H01L21/3065 ; H01L25/065 ; H01L23/00

Abstract:
Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.
Public/Granted literature
- US20150303111A1 DICING WAFERS HAVING SOLDER BUMPS ON WAFER BACKSIDE Public/Granted day:2015-10-22
Information query
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