Invention Grant
- Patent Title: Copper post structure for wafer level chip scale package
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Application No.: US14690570Application Date: 2015-04-20
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Publication No.: US09343415B2Publication Date: 2016-05-17
- Inventor: Chao-Wen Shih , Yung-Ping Chiang , Chen-Chih Hsieh , Hao-Yi Tsai
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/78 ; H01L21/56

Abstract:
In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.
Public/Granted literature
- US20150228597A1 COPPER POST STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE Public/Granted day:2015-08-13
Information query
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