A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC).