Invention Grant
US09349631B2 Method for defining an isolation region(s) of a semiconductor structure
有权
用于限定半导体结构的隔离区域的方法
- Patent Title: Method for defining an isolation region(s) of a semiconductor structure
- Patent Title (中): 用于限定半导体结构的隔离区域的方法
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Application No.: US14504479Application Date: 2014-10-02
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Publication No.: US09349631B2Publication Date: 2016-05-24
- Inventor: Errol Todd Ryan
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/762 ; H01L21/265 ; H01L21/02

Abstract:
Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.
Public/Granted literature
- US20160099168A1 METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE Public/Granted day:2016-04-07
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