Invention Grant
- Patent Title: Integrated circuits and methods of forming the same with multi-level electrical connection
- Patent Title (中): 集成电路和与多级电气连接形成的方法
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Application No.: US13770464Application Date: 2013-02-19
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Publication No.: US09349635B2Publication Date: 2016-05-24
- Inventor: San Leong Liew , Huang Liu
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L23/522

Abstract:
Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.
Public/Granted literature
- US20140232010A1 INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTI-LEVEL ELECTRICAL CONNECTION Public/Granted day:2014-08-21
Information query
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