Invention Grant
- Patent Title: Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures
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Application No.: US14938545Application Date: 2015-11-11
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Publication No.: US09349865B2Publication Date: 2016-05-24
- Inventor: Bich-Yen Nguyen , Mariam Sadaka , Christophe Maleville
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: SOITEC
- Current Assignee: SOITEC
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L23/52 ; H01L27/12 ; H01L29/78 ; H01L27/092 ; H01L29/165

Abstract:
Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
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