Invention Grant
- Patent Title: Package on package (PoP) integrated device comprising a plurality of solder resist layers
- Patent Title (中): 封装的封装(PoP)集成器件包括多个阻焊层
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Application No.: US14447399Application Date: 2014-07-30
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Publication No.: US09355898B2Publication Date: 2016-05-31
- Inventor: Rajneesh Kumar , Houssam Wafic Jomaa , David Fraser Rae , Layal Rouhana , Omar James Bchir
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/528 ; H01L23/532 ; H01L23/495 ; H01L21/48 ; H01L23/498

Abstract:
Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
Public/Granted literature
- US20160035622A1 PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A PLURALITY OF SOLDER RESIST LAYERS Public/Granted day:2016-02-04
Information query
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