Invention Grant
- Patent Title: Power MOS device structure
- Patent Title (中): 功率MOS器件结构
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Application No.: US14130483Application Date: 2013-05-07
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Publication No.: US09356137B2Publication Date: 2016-05-31
- Inventor: Shu Zhang , Yanqiang He , TseHuang Lo , HsiaoChia Wu
- Applicant: CSMC Technologies Fab1 Co., Ltd.
- Applicant Address: CN Wuxi, Jiangsu
- Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Current Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Current Assignee Address: CN Wuxi, Jiangsu
- Agency: Han IP Corporation
- Priority: CN201210142749 20120510
- International Application: PCT/CN2013/075268 WO 20130507
- International Announcement: WO2013/166957 WO 20131114
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L23/00 ; H01L23/482
Abstract:
Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.
Public/Granted literature
- US20140159151A1 Power MOS Device Structure Public/Granted day:2014-06-12
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