Invention Grant
US09362161B2 Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
有权
半导体器件和形成3D双面裸片嵌入式半导体封装的方法
- Patent Title: Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
- Patent Title (中): 半导体器件和形成3D双面裸片嵌入式半导体封装的方法
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Application No.: US14220336Application Date: 2014-03-20
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Publication No.: US09362161B2Publication Date: 2016-06-07
- Inventor: HeeJo Chi , HanGil Shin , NamJu Cho
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00 ; H01L21/44 ; H01L21/768 ; H01L23/528 ; H01L23/498 ; H01L21/48 ; H01L23/538 ; H01L23/00 ; H01L21/56

Abstract:
A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
Public/Granted literature
- US20150270237A1 Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package Public/Granted day:2015-09-24
Information query
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