Invention Grant
US09362350B2 MOS P-N junction diode with enhanced response speed and manufacturing method thereof
有权
具有增强响应速度的MOS P-N结二极管及其制造方法
- Patent Title: MOS P-N junction diode with enhanced response speed and manufacturing method thereof
- Patent Title (中): 具有增强响应速度的MOS P-N结二极管及其制造方法
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Application No.: US14556676Application Date: 2014-12-01
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Publication No.: US09362350B2Publication Date: 2016-06-07
- Inventor: Hung-Hsin Kuo , Mei-Ling Chen
- Applicant: PFC DEVICE HOLDINGS LTD
- Applicant Address: HK Chai Wan
- Assignee: PFC DEVICE HOLDINGS LTD
- Current Assignee: PFC DEVICE HOLDINGS LTD
- Current Assignee Address: HK Chai Wan
- Agency: WPAT, P.C.
- Agent Justin King
- Priority: TW100149213A 20111228
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L29/861 ; H01L29/51 ; H01L29/45

Abstract:
A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a polysilicon oxide layer, a central conductive layer, ion implantation layer, a channel region, and a metallic sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer, and a polysilicon oxide layer formed on the polysilicon structure. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. An ion implantation layer is formed within the guard ring and the central conductive layer. Afterwards, a metallic sputtering layer is formed, and the mask layer is partially exposed.
Public/Granted literature
- US20150084136A1 MOS P-N JUNCTION DIODE WITH ENHANCED RESPONSE SPEED AND MANUFACTURING METHOD THEREOF Public/Granted day:2015-03-26
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