A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.