Invention Grant
US09367370B2 NOC loopback routing tables to reduce I/O loading and off-chip delays
有权
NOC环回路由表,以减少I / O加载和片外延迟
- Patent Title: NOC loopback routing tables to reduce I/O loading and off-chip delays
- Patent Title (中): NOC环回路由表,以减少I / O加载和片外延迟
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Application No.: US14468238Application Date: 2014-08-25
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Publication No.: US09367370B2Publication Date: 2016-06-14
- Inventor: Ezekiel Kruglick
- Applicant: Empire Technology Development LLC
- Applicant Address: US DE Wilmington
- Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee Address: US DE Wilmington
- Agency: Turk IP Law, LLC
- Main IPC: G06F9/54
- IPC: G06F9/54 ; G06F9/455

Abstract:
Technologies are generally described to implement loopback simulation of inter-core messages in multicore processors. In some examples, a multicore processor may execute one or more processes, where each process communicates with other processes on or off the processor. Messages originating from processes on the multicore processor and destined for other processes on the multicore processor may be intercepted by a loopback simulator executing on the multicore processor. The loopback simulator may then redirect the intercepted messages to the destination processes on the multicore processor without the messages leaving the multicore processor.
Public/Granted literature
- US20160055041A1 NOC LOOPBACK ROUTING TABLES TO REDUCE I/O LOADING AND OFF-CHIP DELAYS Public/Granted day:2016-02-25
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