To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory.A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.