Invention Grant
US09368344B2 Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain 有权
包括具有减小的晶格应变的半导体材料层的半导体结构,器件和工程衬底

  • Patent Title: Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
  • Patent Title (中): 包括具有减小的晶格应变的半导体材料层的半导体结构,器件和工程衬底
  • Application No.: US14319029
    Application Date: 2014-06-30
  • Publication No.: US09368344B2
    Publication Date: 2016-06-14
  • Inventor: Chantal Arena
  • Applicant: Soitec
  • Applicant Address: FR Bernin
  • Assignee: SOITEC
  • Current Assignee: SOITEC
  • Current Assignee Address: FR Bernin
  • Agency: TraskBritt
  • Main IPC: H01L21/20
  • IPC: H01L21/20 H01L21/02 H01L21/762 H01L29/06 H01L29/20
Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
Abstract:
Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
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