Invention Grant
US09368590B2 Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
有权
具有自对准无边界源极/漏极触点的绝缘体上硅晶体管
- Patent Title: Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
- Patent Title (中): 具有自对准无边界源极/漏极触点的绝缘体上硅晶体管
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Application No.: US14073581Application Date: 2013-11-06
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Publication No.: US09368590B2Publication Date: 2016-06-14
- Inventor: Susan S. Fan , Balasubramanian S. Haran , David V. Horak , Charles W. Koburger
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agent David A. Cain, Esq.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/70 ; H01L29/423 ; H01L29/49 ; H01L29/66 ; H01L29/786 ; H01L27/12 ; H01L27/088 ; H01L29/78
Abstract:
A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.
Public/Granted literature
- US20140061799A1 SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS Public/Granted day:2014-03-06
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