A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.