Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified.