Invention Grant
US09372993B2 Methods and apparatus to protect memory regions during low-power states
有权
在低功耗状态下保护存储器区域的方法和装置
- Patent Title: Methods and apparatus to protect memory regions during low-power states
- Patent Title (中): 在低功耗状态下保护存储器区域的方法和装置
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Application No.: US14639854Application Date: 2015-03-05
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Publication No.: US09372993B2Publication Date: 2016-06-21
- Inventor: Adrian R. Pearson , Christopher Andrew Thornburg , Steven J. Brown , Peter R. Munguia
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06F21/57
- IPC: G06F21/57

Abstract:
A disclosed example method involves configuring a processor to, when transitioning the processor system to a low-power mode, use a key and a random or pseudo-random value to generate a first signature based on a sample of memory regions to be protected during the low-power mode, the memory regions based on a manufacturer required regions table and a third-party required regions table. The disclosed example method also involves configuring a processor to, during a resume process of the processor system from the low-power mode, generate a second signature based on the sample of the memory regions protected during the low-power mode. The disclosed example method also involves configuring a processor to, when the first signature matches the second signature, cause the processor system to resume from the low-power mode, and when the first signature does not match the second signature, generate an error.
Public/Granted literature
- US20150178500A1 METHODS AND APPARATUS TO PROTECT MEMORY REGIONS DURING LOW-POWER STATES Public/Granted day:2015-06-25
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