Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation
Abstract:
Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.
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