Method of manufacturing semiconductor device

Invention Grant

US09373630B2 Method of manufacturing semiconductor device 有权

Title translation: 制造半导体器件的方法

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Patent Title: Method of manufacturing semiconductor device
Patent Title (中): 制造半导体器件的方法
Application No.: US14989999

Application Date: 2016-01-07
Publication No.: US09373630B2

Publication Date: 2016-06-21
Inventor: Koichi Toba , Hiraku Chakihara , Yoshiyuki Kawashima , Kentaro Saito , Takashi Hashimoto
Applicant: Renesas Electronics Corporation
Applicant Address: JP Tokyo
Assignee: RENESAS ELECTRONICS CORPORATION
Current Assignee: RENESAS ELECTRONICS CORPORATION
Current Assignee Address: JP Tokyo
Agency: Young & Thompson
Priority: JP2013-040061 20130228
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L27/115 ; H01L27/092

Method of manufacturing semiconductor device

Abstract:

To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract(Chinese):

改善具有非易失性存储器的半导体器件。形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。此后，进行热处理以向第一MISFET施加应力。因此，SMT不应用于每个元件，而是被选择性地应用。这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

Public/Granted literature

US20160118394A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2016-04-28

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺