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US09374250B1 Wireline receiver circuitry having collaborative timing recovery 有权
有线接收器电路具有协作定时恢复

Wireline receiver circuitry having collaborative timing recovery
Abstract:
Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
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