Invention Grant
US09384163B2 Non-linear termination for an on-package input/output architecture
有权
用于封装输入/输出架构的非线性终端
- Patent Title: Non-linear termination for an on-package input/output architecture
- Patent Title (中): 用于封装输入/输出架构的非线性终端
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Application No.: US13995110Application Date: 2011-12-22
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Publication No.: US09384163B2Publication Date: 2016-07-05
- Inventor: Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
- Applicant: Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/067019 WO 20111222
- International Announcement: WO2013/095567 WO 20130627
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/14 ; G06F13/36
Abstract:
An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
Public/Granted literature
- US20140089549A1 NON-LINEAR TERMINATION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE Public/Granted day:2014-03-27
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