Invention Grant
- Patent Title: Shallow trench isolation integration methods and devices formed thereby
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Application No.: US14810167Application Date: 2015-07-27
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Publication No.: US09385192B2Publication Date: 2016-07-05
- Inventor: Hongliang Shen , Kyutae Na , Sandeep Gaan , Hsin-Neng Tai , Weihua Tong , Sang Cheol Han , Tae Hoon Kim , Ja Hyung Han , Haigou Huang , Changyong Xiao , Huang Liu , Seung Yeon Kim
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/06 ; H01L21/02 ; H01L27/088

Abstract:
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
Public/Granted literature
- US20150333121A1 SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY Public/Granted day:2015-11-19
Information query
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