Invention Grant
- Patent Title: Capacitive load PLL with calibration loop
- Patent Title (中): 带校准回路的电容负载PLL
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Application No.: US14456064Application Date: 2014-08-11
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Publication No.: US09391626B2Publication Date: 2016-07-12
- Inventor: Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/10 ; H03L7/099 ; H03L7/18 ; H03L7/097 ; H03L7/107
Abstract:
A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
Public/Granted literature
- US20140347110A1 CAPACITIVE LOAD PLL WITH CALIBRATION LOOP Public/Granted day:2014-11-27
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