Invention Grant
- Patent Title: Stacked common gate finFET devices for area optimization
- Patent Title (中): 用于区域优化的堆叠公共栅极finFET器件
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Application No.: US14458228Application Date: 2014-08-12
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Publication No.: US09397101B2Publication Date: 2016-07-19
- Inventor: HariKrishna Chintarlapalli Reddy , Jay Madhukar Shah , Ananth Haliyur Gopalakrishna
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L27/092 ; H01L27/088 ; H01L27/02

Abstract:
A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.
Public/Granted literature
- US20150255461A1 STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION Public/Granted day:2015-09-10
Information query
IPC分类: