Invention Grant
- Patent Title: Latch circuit
- Patent Title (中): 锁存电路
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Application No.: US14678704Application Date: 2015-04-03
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Publication No.: US09397642B2Publication Date: 2016-07-19
- Inventor: Hae-Rang Choi , Mi-Hyun Hwang
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2014-0174945 20141208
- Main IPC: H03K3/356
- IPC: H03K3/356

Abstract:
A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
Public/Granted literature
- US20160164504A1 LATCH CIRCUIT Public/Granted day:2016-06-09
Information query
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