Invention Grant
- Patent Title: Cooperative thread array reduction and scan operations
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Application No.: US14025482Application Date: 2013-09-12
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Publication No.: US09417875B2Publication Date: 2016-08-16
- Inventor: Brian Fahs , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F15/00 ; G06F9/38 ; G06F9/52

Abstract:
One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.
Public/Granted literature
- US20140019724A1 COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS Public/Granted day:2014-01-16
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