Invention Grant
- Patent Title: Thread scheduling based on predicted cache occupancies of co-running threads
- Patent Title (中): 基于预测的并行线程缓存占用的线程调度
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Application No.: US13853734Application Date: 2013-03-29
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Publication No.: US09430277B2Publication Date: 2016-08-30
- Inventor: Puneet Zaroo , Richard West , Carl A. Waldspurger , Xiao Zhang
- Applicant: VMware, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: VMware, Inc.
- Current Assignee: VMware, Inc.
- Current Assignee Address: US CA Palo Alto
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06F9/50 ; G06F11/34 ; G06F12/08

Abstract:
A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.
Public/Granted literature
- US20130232500A1 CACHE PERFORMANCE PREDICTION AND SCHEDULING ON COMMODITY PROCESSORS WITH SHARED CACHES Public/Granted day:2013-09-05
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