Invention Grant
- Patent Title: Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement
- Patent Title (中): 通过牺牲源/漏极区域和栅极替换在晶体管沟道中引入应力的增强方法
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Application No.: US14950833Application Date: 2015-11-24
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Publication No.: US09431538B2Publication Date: 2016-08-30
- Inventor: Shay Reboh , Pierre Morin
- Applicant: Commissariat a l'energie atomique et aux energies alternatives , STMICROELECTRONICS, Inc.
- Applicant Address: FR Paris US TX Coppell
- Assignee: Commissariat a l'energie atomique et aux energies alternatives,STMICROELECTRONICS Inc.
- Current Assignee: Commissariat a l'energie atomique et aux energies alternatives,STMICROELECTRONICS Inc.
- Current Assignee Address: FR Paris US TX Coppell
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1461459 20141125
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L29/16 ; H01L29/161 ; H01L29/165 ; H01L29/66 ; H01L29/06
Abstract:
Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.
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