Invention Grant
- Patent Title: Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
- Patent Title (中): 具有自对准接触工艺流程和制造方法中线路电容降低的集成电路
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Application No.: US14616226Application Date: 2015-02-06
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Publication No.: US09443738B2Publication Date: 2016-09-13
- Inventor: Hui Zang , Balasubramanian Pranatharthiharan
- Applicant: GLOBALFOUNDRIES Inc. , INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: KY Grand Cayman US NY Armonk
- Assignee: GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: KY Grand Cayman US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Jacquelyn A Graff
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/283 ; H01L21/28
Abstract:
Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one sacrificial gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; removing the at least one sacrificial gate; forming at least one gate; and forming at least one small contact over the first contact region and the second contact region. An intermediate semiconductor device is also disclosed.
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