Invention Grant
US09443744B2 Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
有权
具有高效热路径和相关方法的堆叠式半导体管芯组件
- Patent Title: Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
- Patent Title (中): 具有高效热路径和相关方法的堆叠式半导体管芯组件
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Application No.: US14330934Application Date: 2014-07-14
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Publication No.: US09443744B2Publication Date: 2016-09-13
- Inventor: Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/56 ; H01L25/065 ; H01L25/16 ; H01L25/00 ; H01L23/04 ; H01L21/50 ; H01L23/36 ; H01L23/367 ; H01L21/48
Abstract:
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Public/Granted literature
- US20160013115A1 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS Public/Granted day:2016-01-14
Information query
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