Invention Grant
- Patent Title: Pin arrangement and electronic assembly
- Patent Title (中): 引脚布置和电子组装
-
Application No.: US14551094Application Date: 2014-11-24
-
Publication No.: US09444165B2Publication Date: 2016-09-13
- Inventor: Sheng-Yuan Lee
- Applicant: VIA Technologies, Inc.
- Applicant Address: TW New Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei
- Agency: Jianq Chyun IP Office
- Main IPC: H01R12/00
- IPC: H01R12/00 ; H01R12/77 ; H05K1/02 ; H05K1/14 ; H01R13/6473 ; H01R13/6471 ; H05K1/11

Abstract:
A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.
Public/Granted literature
- US20160079694A1 PIN ARRANGEMENT AND ELECTRONIC ASSEMBLY Public/Granted day:2016-03-17
Information query